The maximum operating speed of current semiconductor devices is limited by the time delay factor T=RC of metal lines, where R is the resistance of the metal lines and C is the capacitance of the dielectric insulating material surrounding the metal lines. As the minimum feature size of integrated circuits continues to shrink, the metal lines become thinner and more densely packed, resulting in greater resistance in the metal lines and larger inter-metal capacitance, and therefore a longer time delay. By changing to different materials, i.e., higher conductivity material for the metal lines and lower permittivity (low-k) dielectric for the insulating material, device geometry can continue to shrink without adversely impacting the maximum operating speed. This has prompted the switch from aluminum and silicon dioxide to copper and low-k dielectrics such as organosilicate glass in the backend process flow for manufacturing many current and future semiconductor devices.
The switch from aluminum/oxide to copper/low-k involves a variety of fundamental changes in the backend manufacturing process flow. Since it is difficult to etch copper, new approaches such as “damascene” or “dual damascene” processing are required. Copper damascene/dual-damascene is a process where vias and trenches are etched into the insulating material. Copper is then filled into the vias and trenches and sanded back so the conducting materials are only left in the vias and trenches. Among the many challenges presented by this process, etching trenches or vias in low-k dielectrics can be tricky due to the more complicated chemical composition of the dielectric material and the many different kinds of low-k dielectric materials available. The etch chemistry for etching a low-k dielectric material may have to be tailored to match up with the amount of carbon, hydrogen, silicon, fluorine and oxygen in the material.
The ratio of the rate of etching a low-k dielectric layer to the rate of etching one of the adjacent layers of other materials is called etching selectivity. A photoresist layer is typically used to mask the low-k dielectric layer during the etching process. As the feature sizes continue to shrink, the photoresist mask becomes thinner in order to meet lithography-related challenges posed by smaller feature sizes. The thinner resist requires tighter control on the dielectric etch selectivity. However, like photoresist, many low-k dielectric materials also contain some carbon and hydrogen, making it harder to meet the selectivity requirement. Therefore, compared with traditional dielectric etching processes, selectively etching low-k dielectric materials requires more precise tuning of the process chemistry and process parameters.
Another problem associated with etching low-k dielectrics is the dependence of the low-k dielectric etch rate upon pattern density and topographic dimensions of etched features (e.g. vias and trenches), which is known as etch rate microloading, or microloading. The etch rate microloading is a measure of the difference in etch rate in features having different sizes, and is calculated as a percent value of the difference between etch rate in a larger feature and etch rate in a smaller feature divided by the etch rate in the larger feature. It has been noted that microloading increases as the size of an opening of the small feature decreases and as the aspect ratio of the small feature increases.